Course Name: SoC Verification
Prerequisites: VLSI Design, Design of Application-Specific Integrated Circuits
With rapid strides in semiconductor processing technologies, the density of transistors on the die is increasing in line with Moore’s law which in turn is increasing the complexity of the whole SoC design. A typical SoC incorporates a large number of heterogeneous IP cores. Veriﬁcation is the process of checking if the transformation from architectural speciﬁcation to design implementation is correct. Veriﬁcation involves creating the following components: (i) a test-plan that identiﬁes the conditions to be veriﬁed, (ii) a test-case that generates the stimuli to verify the conditions identiﬁed, and (iii) a test-bench that applies the stimuli and monitors the output from the design. Veriﬁcation usually consumes upto 70% of the total design time. Therefore, SoC verification is a major challenge that needs to be mastered by design engineers to minimize iteration time and data volume.
This course presents various state-of-the-art verification techniques used to ensure thorough testing of the SoC design. Also, the use of simulation, emulation, assertion-based verification, and hardware/ software co-verification techniques will be discussed.